View ADM6308_1548847.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

admtek incorporated partnership now and future olive family adm 63 08 - eight -po rt 10/100m ethernet switch controller admtek incorporate 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/ 25 version : 1.10 admtek incorporated confidential overview ADM6308, a single chip, is a 10/100mbps eight-port stand-alone switching controller with built-in data buffer memory which provides low cost and simple solution though a high integration design. eight reduced mii interfaces are designed for 10base/100base ports. mac controller, switch engines and data buffer memory are built-in. the chip can fit to desktop or soho applications, and each 10/100m port directly connects either 10base or 100base devices. additionally, ADM6308 breaks the distance limitation of 10base or any class 100base repeaters, and increases throughput. features non-blocking eight-port 10/100m switching controller with mac controller and switching engine included low cost and a simple solution for 100base-tx, 100base-fx, and 10base applications. configurable 10/100base reduced mii interfaces and 1mii+ 7rmii mode provided. the single clock input, 50m, for rmii and system speed auto negotiation function for all ports store-and- forward operation support. full line speed capability of 14880 packet/sec for 10m and 148810 packet/sec for 100m, with no hol blocking. broadcast storming prevention support 4 groups port-based vlan. full-duplex (ieee802.3x) and three-way half-duplex flow control ( back pressure). data buffer ssram embedded , cos support: port-based, vlan tag, tcp/ip tos/ds. intelligently back-pressure and flow control turned on/off in the port with priority frames buffer management included. 93c46 eeprom interface or dynamic configured by 8051 buffer full and faulty led provided. bridging functions such as: u local mac address filtering. u crc or direct mapping hashing schemes for better address coverage. u short routing decision time. u aging function included with configurable aging time. u embedded 1k entries of address table. low power 2.5 v cmos technology with 3.3v tolerance i/o 100-pins plastic quad flat package.
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 2 block diagram example of system diagram n-way monitor eeprom i/f configuration link table data buffer control & fabric tx dma rx dma tx dma rx dma tx dma rx dma from port 0 to port 7 from port 0 to port 7 from port 0 to port 7 tmac rmac tmac rmac tmac rmac rmii rmii rmii ADM6308 8-port switch eeprom (option) quad phyceiver quad phyceiver transformer transformer osc
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 3 pin diagram rxd2[0] rxdv6 rxd6[0] rxd6[1] vss txe7 txd7[0] txd7[1] vddi rxdv7 rxd7[0] rxd7[1] vss mdc vddo mdio qfled# vss eesk/xfc# eecs/bp1 eedi/bp0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 olive plus ADM6308 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 rxd2[1] rxd1[1] rxdv2 txd2[1] txd2[0] txe2 vddo rxd1[0] vss rxdv1 vddi txd1[1] txd1[0] txe1 vss rxd0[3] rxd0[2] rxd0[1] rxd0[0] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 30 vss txe3 txd3[0] txd3[1] rxdv3 vddi rxd3[0] rxd3[1] vss refclk vddo txe4 txd4[0] txd4[1] rxdv4 rxd4[0] rxd4[1] vss vss txe5 txd5[0] txd5[1] vddi rxdv5 rxd5[0] rxd5 [1] vddo txe6 txd6[0] txd6[1] 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 77 76 vss txd0[1] txd0[0] txe0 vddo col0 crs0 vddi mii# test[1] test[0] vss reset# vss high _port[7] high _port[6] high _port[5] high _port[4] vddi high _port[3] high _port[2] high _port[1] high _port[0] recall eedo/na16# rxdv0 rxc0 txc0 txd0[3] txd0[2]
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 4 pin descriptions pin name pin # type descriptions eeprom interface eedo 51 i eedo: data output of serial eeprom. internally pull up (50k ohm). inputs configuration information to ADM6308. eedi 50 bi 4ma eedi: data input of serial eeprom. internally pull down (50k ohm). ADM6308 outputs data to eeprom eesk 48 bi 4ma eesk: clock input of serial eeprom. internally pull up. ADM6308 outputs clock signal to eeprom eecs 49 bi 4ma chip select of serial eeprom. internally pull down. eeck/s:50ns, h:0ns reduced mii interface txe0 txe1 txe2 txe3 txe4 txe5 txe6 txe7 72, 86 95, 2 12, 20 28, 35 o 8ma transmit enable. txe0~7 shows that ADM6308 is presenting the recovered and decoded data on the txd0~7[1:0]. txe0~7 indicates that the mac is presenting di-bits on txd0~7[1:0] on the reduced mii for transmission. txe0~7 shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are presented to the reduced mii. txe0~7 shall be negative prior to the first refclk rising edge following the final di-bit of a frame. txe0~7 shall transition synchronously with refclk. txd0[1:0] txd1[1:0] txd2[1:0] txd3[1:0] txd4[1:0] txd5[1:0] txd6[1:0] txd7[1:0] 74, 73 88, 87, 97, 96 4 , 3 14, 13 22, 21 30, 29 37, 36 o 4ma transmit data. these bundle signals are output from ADM6308 to reduced mii connecting device. these signals are transited synchronously with the rising edge of txe0~7. when txe0~7 is being asserted, for each period of txe0~7, ADM6308 drives the recovered and encoded data into txd0~7[1:0] for transmission. while txe0~7 is de-asserted, the txd0~7[1:0] will have no effect upon the reduced mii connecting device. txd0~7[1:0] shall transition synchronously with refclk. when txe0~7 is being asserted, txd0~7[1:0] is accepted for transmission by the phy. txd0~7[1:0] shall be ? 00 ? to indicate idle when txe0~7 is de-asserted. values of txd0~7[1:0] other than ? 00 ? when txe0~7 is de-asserted are reserved for out-of-band signaling (to be defined). values other than ? 00 ? on txd0~7[1:0] while txe0~7 is de-asserted shall be ignored by the phy. txc0 78 bi 4ma transmit clock for port0 mii mode. txd0[3:2] 77, 76 o 4ma transmit data for port0 mii mode.
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 5 rxdv0 rxdv1 rxdv2 rxdv3 rxdv4 rxdv5 rxdv6 rxdv7 80, 90 98, 5 15, 24 31, 39 i carrier sense and receive data valid. rxdv2, rxdv3, rxdv5, rddv6, rxdv7 internally pull down. rxdv0~7 shall be asserted by the phy when the receiver is not idle. the specific definition of idle for 10base-t and 100base-x is contained in ieee 802.3 and ieee 802.3u. rxdv0~7 also shows that the receiving data is presented on the rxd0~7[1:0] from reduced mii connecting device. rxdv0~7 is being asserted asynchronous on detection of carrier due to criteria relevant to the operating mode. that is, in 10base-t mode, when squelch is passed or in 100base-x mode when 2 non-contiguous zeroes in 10 bits are detected, carrier is said to be detected. loss of carrier shall result in the de-assertion of rxdv0~7 synchronous to the cycles of refclk which presents the first di-bit of a nibble onto rxd0~7[1:0]. if the phy has additional bits to be presented on rxd0~7[1:0] following the initial de-assertion of rxdv0~7, then the phy shall assert rxdv0~7 on cycles of refclk which present the second di-bit of each nibble , and de-assert rxdv0~7 on cycles of refclk which present the first di-bit of a nibble. during a false carrier event, rxdv0~7 shall remain asserted for the duration of carrier activity. the data on rxd0~7[1:0] is considered valid once rxdv0~7 is being asserted. however, since the assertion of rxdv0~7 is asynchronous relative to refclk, the data on rxd0~7[1:0] shall be ? 00 ? until proper receive signal decoding takes place. rxd0[1:0] rxd1[1:0] rxd2[1:0] rxd3[1:0] rxd4[1:0] rxd5[1:0] rxd6[1:0] rxd7[1:0] 82, 81 93, 92 100, 99 8 , 7 17, 16 26, 25 33, 32 41, 40 i receive data. rxd 2[1:0], rxd 3[1:0], rxd 5[1:0], rxd 6[1:0], rxd 7[1:0] internally pull down. these bundle signals are input from the reduced mii connecting device. rxd0~7[1:0] shall transition synchronously to refclk. for each clock period in which rxdv0~7 is being asserted, rxd0~7[1:0] transfers two bits of recovered data from the phy. in some cases (e.g. before data recovery or during error conditions) a pre-determined value for rxd0~7[1:0] is transferred instead of the recovered data. rxd0~7[1:0] shall be ? 00 ? to indicate idle when rxdv0~7 is de-asserted. values of rxd0~7[1:0] other than ? 00 ? when rxdv0~7 as recovered from rxdv0~7 is de-asserted are reserved for out-of- band signaling (to be defined). values other than ? 00 ? on rxd0~7[1:0] while rxdv0~7 as recovered from rxdv0~7 is de-asserted shall be ignored by the mac. upon assertion of rxdv0~7, the phy shall ensure that rxd0~7[1:0]= ? 00 ? until proper receive decoding takes place. these pins will be in high impedance, and ignore the input when rxdv0~7 is negative. rxc0 79 bi 4ma receive clock for port0 mii mode. rxd0[3:2] 84, 83 bi 4ma receive data. rxd 0[3:2] internally pull down for port0 mii mode .. crs0 69 bi 4ma carrier sense for port0 mii mode. col0 70 bi 4ma collision for port0 mii mode. mii# 67 i internally pull up. active low. this pin can be tied to low for reversing the reduced mii to mii (port0 only). there is an internal pull high for default configuration. ADM6308 also provides the 1mii+7rmii mode for customer specific requirement. the default address ids for phy are the consecutive numbers as follows: 7(for port 0 mii), 8, 9, 10, 11,12,13,14 ,(for port 1~7 rmii). p.s.: the id addresses must be the consecutive numbers, otherwise, ADM6308 won ? t recognize the id address for phy.
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 6 mdc 43 o 8ma management data clock. provides the reference clock for the mdio signal mdio 45 bi 8ma management data input/output. this pin provides the channels for ADM6308 and transceivers to transfer the control information and status. led display qfled# 46 tri 8ma buffer full or faulty led display. this occurs when the packet is lost and flow control is disabled. or, if flow control is enabled and jam or pause frames are sent, buffer full led will flash. if it is found faulty, the led will always be on. (see led function description) high priority frame high_port[0] high_port[1] high_port[2] high_port[3] high_port[4] high_port[5] high_port[6] high_port[7] 53 54 55 56 58 59 60 61 bi priority setting for port0~port7. internally pull down. high = high priority configuration bp0 bp1 50 49 i back pressure mode. internally pull down. the bp0~1 modes define 4 different back- pressure methods. each bpa1~3 has different algorithm described in eeprom section. the following shows ADM6308 configuration of back-pressure. bp1 bp0 0 0 back pressure disable 0 1 bpa1 (back pr essure algorithm 1) enable 1 0 bpa2 (back pressure algorithm 2) enable 1 1 bpa3 (back pressure algorithm 3) enable na16# 51 i not aborted after continuous 16- times of collision if pull down. internally pull up. xfc# 48 i full duplex flow control. internally pull up. when 802.3 x flow control is disable, no pause frame will be sent. (default) miscellaneous refclk 10 i clock reference input of 50mhz reduced mii. synchronous clock reference for receiving, transmitting, and control interface. reset# 63 i reset#. active low. for power on reset to initiate ADM6308 and let all the state machines and statuses enter the initial and default state. besides, all the led will be turned on when power is on or ram testing failed. recall 52 i whenever the level is changed, ADM6308 recalls eeprom or 8051-like controller to get configuration data. internally pull down. test[0] 65 i test mode. internally pull down test[1] 66 i test mode. internally pull down power vddi 6, 23, 38, 57, 68, 89 2.5v vddo 11, 27, 44, 71, 94 3.3v
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 7 vss 9, 19, 42, 64, 75, 91 1, 18, 34, 47, 62, 85
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 8 eeprom content the eeprom setting must be in 16-bit mode. offset content description 00h check pattern must be set to 017c 01h system configuration bit 3~0 ? inter frame gap in half-duplex mode only. default is zero (96 bit- time). bit 3 is a sign bit. when bit 3 is zero, it means negative. bit 0 ~ 2 present decimal value of bit time (times four). for example, 1010, the ifg is equal to 96 + 2 x 4 = 104. bit 7~4 ? configurable aging time. default is 300 sec. when bit 7 is one, fast aging time (15 sec) is set. if all zero, aging timer is disabled. for the other value, list below. bit 7 bit 6 bit 5 bit 4 0 0 0 1 aging time is 300 sec (d efault) 0 0 1 0 aging time is 600 sec 0 0 1 1 aging time is 1200 sec 0 1 0 0 aging time is 2400 sec 0 1 0 1 aging time is 4800 sec 0 1 1 0 aging time is 9600 sec 0 1 1 1 aging time is 38400 sec bit 9~ 8 ? broadcast storming mode. this mode is only for broadcast destination address, ff ff ff ff ff ff. bit 9 bit 8 0 0 disable (default) 0 1 256 blocks 1 0 192 blocks 1 1 128 blocks bit 11 ~ 10 ? maximum length of the data field of frame format. bit 11 bit 10 0 0 maximum length is 1536 bytes (default) 0 1 maximum length is 1518 bytes 1 0 maximum length is 1522 bytes 1 1 reserved bit 12 ? continuous 16-time collision abort per packet is enabled if set to zero. default is zero. eeprom setting has higher priority than pin ? s. bit 13 ? hashing algorithm selection. if zero, direct mapping algorithm is selected. otherwise, crc hashing algorithm is adopted. default is zero. bit 14 ? over written address. default is zero, which means over written address is not allowed whenever the same addresses entry condition occurred after hashing algorithm implementation finished. bit 15 - must be set to zero. 02h back pressure and back- off bit 2 ~ 0 - must be ? 0 0 1 ? . bit 6 ~ 4 - must be ? 1 0 1 ? . bit 11 ~ 8 ? jam number for bp algorithm 1 bit 13 ~ 12 ? bp mode 00 : disable bp 01 : bp jam 10 : bp jam all
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 9 11 : bp carrier bit 14 ? 1 (default) bit 15 ? 0 (default) 03h auto-negotiation monitor bit 7 ~ 0 ? n-way monitor disable port [7:0]. 0 : enable (default) bit 15 ~ 8 - port disable port [7:0]. 0 : enable (default) 04h speed and half/full duplex setting when n-way monitor disable bit 7 ~ 0 ? full/half operation. each bit presents dedicated port number. lower bit is intended for smaller port number. 1 stands for full duplex, 0 for half duplex. bit 15 ~ 8 ? speed setting for port [7:0]. speed operation, 10mbps or 100mbps. one bit per port. 1 stands for 100mbps, 0 for 10mbps. 05h 4 port-groups operation (1) bit 7 ~ 0 ? port group ii [7:0], default is 00h. bit 15 ~ 8 ? port group i [7:0], default is ffh. 06h 4 port-groups operation (2) bit 7 ~ 0 ? port group iv [7:0], default is 00h. bit 15 ~ 8 ? port group iii [7:0], default is 00h. 07h 802.3x flow control and back pressure enable bit 7 ~ 0 ? per port bp enabled port [7:0], 1 stands for enable (default). if enabled, it must be in half duplex mode. bit 15 ~ 8 ? per port 802.3x flow control enabled port [7:0]. 0 stands for disable (by pin) 08h 802.3x flow control bit 7 ~ 0 ? force 802.3x flow control on (ignore an) port [7:0]. if enabled, it must be in full duplex. 0 stands for disable (default). bit 15 ~ 8 ? write fc-bit (10 th bit) of mii register4 port [7:0], 1 stands for enable (default). 09h reserved must be set to 112h 0ah reserved must be set to 132h 0bh reserved must be set to b2h 0ch reserved must be set to d2h 0dh reserved must be set to 150h 0eh reserved must be set to 170h 0fh reserved must be set to 150h 10h reserved must be set to 170h 11h reserved must be set to e8h 12h reserved must be set to c8h 13h reserved bit 7~0 - must be set to 18h bit 15~8 ? must be set to 0ch 14h priority frame operation bit 7 ~ 0 ? auto turn off bp/fc, if get priority packet port [7:0]. 0 stands for disable (default) bit 11 ~ 8 ? round-robin(sequential) number of high and low priority frame for example as follows: bit11 bit10 bit9 bit8 0 0 0 0 weighted ratio is unlimited 0 0 0 1 weighted ratio 1:1 0 0 1 0 weighted ratio 2:1 1 0 0 0 weighted ratio 8:1 (default) bit 13 ? must be set to 0. bit 14 ? must be set to 0. bit 15 ? priority is enabled, 1 stands for enable (default). 15h tos priority port bit 15 ~ 8 ? set tos priority port [7:0], 0 stands for no check (default). one bit per port. e.g. bit 8 for port 0 and bit 15 for port 7. 16h vlan bit 7 ~ 0 - set vlan priority port [7:0], 0 stands for no check (default). one bit per port. e.g. bit 0 for port 0 and bit 7 for port 7.
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 10 bit 15 ~ 8 ? first, ADM6308 will check the specific bits recorded in the type field of packet format to verify the vlan status of packets, then set the threshold of vlan. the default of threshold is 4. if threshold ? 4, the packet is high priority. 17h tos bit map bit 15 ~ 0 - tos bit map [63:48]( tos_pri)( tos_pri_drop), default is 0. first, ADM6308 will check the specific bits recorded in the type field of tcp/ip packet format, to verify the tos status of packets, then implement the bits mapping for priority setting of each port. 18h tos bit map bit 15 ~ 0 - tos bit map [47:32]( tos_pri)( tos_pri_drop), default is 0. first, ADM6308 will check the specific bits recorded in the type field of tcp/ip packet format, to verify the tos status of packets, then implement the bits mapping for priority setting of each port. 19h tos bit map bit 15 ~ 0 - tos bit map [31:16]( tos_pri)( tos_pri_drop), default is 0. first, ADM6308 will check the specific bits recorded in the type field of tcp/ip packet format, to verify the tos status of packets, then implement the bits mapping for priority setting of each port. 1ah tos bit map bit 15 ~ 0 - tos bit map [15: 0]( tos_pri)( tos_pri_drop), default is 0. first, ADM6308 will check the specific bits recorded in the type field of tcp/ip packet format, to verify the tos status of packets, then implement the bits mapping for priority setting of each port. 1bh phy operation (1) bit 4 ~ 0 ? phy rewrite register address. these bits present phy register address selection. bit 7 ? phy rewrite. default is zero ( disable ). bit 12 ~ 8 ? phy start id. default is 00h. this means phy ids range from 00 h to 07h in sequence if default value is set. remember start id always has to remain consistent with the first port id setting in phy. bit 15 ~ 13 ? n/a. 1ch phy operation (2) bit 15 ~ 0 ? phy rewrite data. after phy rewrite register address is selected, the register in each port is set to rewrite data. 1dh reserved must be set to 10dh
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 11 function description ADM6308 is a high performance, low cost, quality assurance 8-port fast ethernet controller dedicated to 8-port switch solutions. this chip operates at 50mhz and fully complies with ieee 802 series specifications, including mac and physical layers. the switch operations include forwarding scheme, packet filtering, address learning, buffer management, led display, etc. packets from reduced mii interface should be stored in the memory. then, source address learning, packet filtering, and retransmission to known or unknown port(s) is implemented based on real application. reset and restart when ADM6308 is on, it starts in embedded memory self-test mode. port interface 10/100mbps reduced mii interface each port of ADM6308 supports reduced mii interfaces, which uses six pins, txe0~7, txd0~7[1:0], rxdv0~7, rxd0~7[1:0]. feature setting can be chosen by configuration pin. the rmii specification has the following characteristics: 1. it supports 10mbps and 100mbps data rates 2. a single clock reference sources from the mac to phy (or from an external source) 3. it provides independent 2-bit wide ( di-bit) transmit and receive data paths rmii specification signals signal name direction with respect to phy direction with respect to the mac usage refclk input input or output synchronous clock reference for receive, transmit and control interface rxdv output input carrier sense rxd[1:0] output input receive data txe input output transmit enable txd[1:0] input output transmit data all detail pin description (please see pin assignment). in addition, ADM6308 also provides the mii mode at port 0 only. the relevant settings are described in the previous pages of pin description. buffer management the buffer memory is embedded in ADM6308 for eight port switch operations, which are designed based on output queuing and dynamic shared memory management architecture. media access control ADM6308 implements all functions of ieee 802.3 mac protocol such as frame formatting, collision handling, etc. ADM6308 generates 56-bit preamble and start of frame delimiter while a packet is being sent. in half-duplex mode, listening before transmitting allows to prevent traffic jam. whenever a collision occurs, packet will be delayed for a random time, then be re- sent. eeprom or dynamic configured by 8051 eeprom is a configuration option for 8-port switch setting. this setting can also be called through recall pin triggered by the controller like 8051. 1. eeprom recall after power-on is reset.
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 12 2. the configuration can be changed without a reset. toggling the ? recall ? pin will read the eeprom again, while 8051 will emulate the signal like eeprom operation modes reduced mii interface to phys or transceivers can operate at 10/100mbps full or half-duplex mode. to keep a consistent operation speed, these two parts (phy and switching controller) will be automatically adjusted the mode through mdc/mdio pins. ADM6308 also provides fixed speed and operation mode configured by eeprom, and dynamic configuration by the controller like 8051. all modes support full wire speed operations without any interference. automatic address learning, forwarding, and filtering function address recognition ADM6308 provides 1kbytes embedded mac address table to implement the address recognition. self-learning bridge function is based on source address packets field. look-up table and two different hashing algorithms strengthen the bridge ability with high performance assurance. configurable aging time is also supported. an entry of hashing table is calculated by 32-bit polynomial (called crc hashing function) or direct mapping (called simple hashing function), as well as mac address (called input data). direct mapping function is allocated the lowest 10 bits of sa/da address as buffer address entry. hashing function selection is set to bit 13 of offset 01h in eeprom. each da (destination address) passes through hashing function and gets a 10-bit entry point of embedded sram. if the record is empty, the packet is broadcast, treated as an unknown frame. otherwise, the record is read, then mac address in storage and da from current packet are compared. if the two addresses are the same, a port number is decided, and the packet is forwarded to the assigned port. if the two addresses are different, the incoming packet is also treated as an unknown packet. a broadcast packet will pass through the other ports without address recognition. learning process address learning process is composed of sa packets and a hashing function described above. for each incoming packet, ADM6308 will check and see whether the packet is errorless and whether the content of the entry address in sram is assigned. if it is, the packet will be compared to source mac address, and the port number. if both fields match the packet information, aging status is revised to new learnt address. if mac addresses matches, but the port number is different, port number is re-assigned. when the entry collides, the new sa address is ignored and the record keeps the old one. last possibility, if the record is free, mac address and port number of the incoming packet are stored. the following diagram describes the general operations of address learning and recognition. forwarding scheme ADM6308 forwarding scheme adopts store-and-forward method. each determined outgoing packet in the buffer of incoming port is directly sent to the assigned port. the forwarding scheme of unknown packets is treated the same as broadcast packet. ADM6308 also requires first- in-first-out service, to prevent packets disorder. ieee 802.3 congestion control in half duplex operation, ADM6308 supports back pressure feature. when the buffer is full, jam packet or 802.3x control frame is sent to the connected segment, which is called back - pressure. ADM6308 implements alternative back - pressure based on either one of three algorithms described in eeprom section. if free blocks in the buffer memory match or are below the threshold, jam packet is directly transmitted regardless of routing decision. crc or direct mapping hashing function da or sa [0:9] address entry point aaa-1 aaa aaa+1 address look-up table fig. 1 address learning and recognition
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 13 in full duplex flow control, ADM6308 follows ieee 802.3x standard. the delay time in pause frame can be set to zero or to the maximum value. the feature allows ADM6308 to handle remote-side pause frame. in full duplex flow control, the state machine and threshold values are described in eeprom, too. the diagram shown above is ieee 802.3x pause frame format. all fields are listed below. destination address: destination mac address (generally the content is 0x0180c2000001) source address: source mac address type: the pause frame type is 0x8808 opcode : the value is fixed, 0x0001 (pause operation) pause time: number of slot-time pad: all zeroes in ADM6308, if a pause frame is received from a certain port with da 0x0180c2000001 or 0xffffffffffff, ADM6308 will stop the ports transmission of packets and the timer until timeout or another pause frame with zero time. if the buffer is full and in full duplex mode, ADM6308 will send pause frame with the maximum delay time, to defer receiving packet. when enough buffer is released, pause frame with zero delay is sent. auto-negotiation operations when mdc/mdio pins do not communicate with transceivers, ADM6308 can be set to 10/100mbps or half/full duplex mode independently. otherwise, ADM6308 can adjust its speed itself according to auto-negotiation with phyceiver. priority frame ( cos) operations ADM6308 can set the packets as high priority as follows: port number (set by pin), vlan tag, tcp/ip tos/ds (both can be set by eeprom or 8051-like controller) and the scheme of weighted round robin. the priority setting by port means that all the packets received by the port will be priority frames; ADM6308 can also judge the priority of frames by checking the specific bits of vlan tag or tcp/ip tos/ds included in the frame format. ADM6308 will check the specific bits recorded in the type field of packet format to ensure the vlan or tcp/ip tos/ds status of packets, then set the threshold of vlan or tcp/ip tos/ds to declare the priority of packets. in addition, the scheme of weighted round robin is used for judging the high and low priority of frames, which utilizes the notion of weighted ratio of priority frame vs. normal frame to decide the frame priority level. when the port receives the priority frame, back pressure & 802.3x flow control will be turned off until no priority frame occurs within 1 or 2 seconds, then turn on back pressure and 802.3x flow control again. vlan and broadcast storming prevention ADM6308 supports vlan function to ease the administration of logical groups of stations that can communicate as if they were on the same lan, and move, add or change in numbers of these groups. ADM6308 also supports 4 port-groups scheme to effectively prevent the broadcast storming from interfering with the whole transmission efficiency between ports. the 8 ports can be divided into 4 groups while broadcast storming is starting, then the broadcast frames to be transmitted to the destination port belonging to other groups will be prohibited. during this time, the ports belonging to different groups are independent. only the destination port of broadcast frames in the same group will be allowed. furthermore, the scheme of port-group dividing is very flexible. the overlapped port-groups are allowed during some operations, for example, one port can be shared by two groups, and all the other operations between these two groups remain independent except for the overlapped port. only the overlapped port could use the same da for two different vlan port-groups. 6 octets 6 octets 2 octets 2 octets 2octets 42 octets destination address source address type opcode pause time pad fig 2 ieee 802.3x pause frame format
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 14 inter-frame gap ifg is the idle time between any two continuous packets from the same port. the default value of 10mbps is 9.6usec and 0.96usec for 100mbps. ifg mode can only be from crs to txe. mdc, mdio interface fig. 3 a specific application of serial management interface there are two pins of serial management interface for ADM6308. mdc (management data clock) is an input pin. it functions mii interface of phy device. the mdio pin is a bi-directional i/o pin of mii interface to phy device. if the following conditions are true, ADM6308 will set bit 1 of register 4 to 1 and bit 9 of register 0 to 1 in connected transceiver. first, ieee 802.3x flow control is enabled. then, the port number of flow control write in eeprom offset 05h is enabled. then, ADM6308 is in full duplex simultaneously with the transceiver. after write operation through mdio, auto-negotiation is restarted and ADM6308 can gain the information of remote 802.3x flow control. finally, the ultimate operation of flow control is set. led interface ADM6308 supports one led only assigned to pin 46 , which represents the buffer as full and ram test fault. when ADM6308 is reset, led is off. while in testing mode, led is on. if the test for embedded data buffer & address table fails, the led will flash once, for about 1.6 sec, and then stay on. next, if the testing for the other embedded memory fails, led will flash twice, for about 1.6sec. after ram tests are successful, led status is down, for about 3.2sec. minimum. if back -pressure or full duplex flow control is set, the buffer full led will flash every 200ms, then stay on for 3.2sec based on jam packet or if pause frame is sent. if an arrival packet is dropped, the led will flash every 50ms, then stay on for 3.2sec. olive plus mdc mdio phy mdc mdio
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 15 absolute maximum ratings supply voltage( vcc) -0.5 v to 2.7 v input voltage -0.5 v to vcc + 0.3 v output voltage -0.5 v to vcc + 0.3 v storage temperature -65 c to 150 c(-85 f to 302 f) ambient temperature 0 c to 70 c(32 f to 158 f) esd protection 2000v dc specifications parameter description condition min typical max units vcc supply voltage 2.3 2.5 2.7 v icc power supply vcc = 2.5v 420 ma vil input low voltage -0.5 0.8 v vih input high voltage 2.0 3.8 v iil input low leakage current vin = 0.8v -10 10 ua iih input high leakage current vin = 2.0v -10 10 ua vol output low voltage iout =2~8ma . 0.4 v voh output high voltage iout =-2~-8ma 2.4 v cinp input pin capacitance 5 8 pf lpinp pin inductance n/a nh ac specifications eeprom timing parameter description condition min max units t21 eeck (50% duty cycle) clock = 50mhz 620 ns t22 eecs/eedi delay from falling of eeck clock = 50mhz 100 ns t24 idle time of two eecs clock = 50mhz 4000 ns t25 eedo valid before rising of eeck 100 ns t26 eedo hold after rising of eeck 30 ns eeck eedi t21 t22 t24 eecs eedo t25 t26
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 16 rmii transmit and receive timing symbol parameter min type max units ref_clk frequency 50 mhz ref_clk duty cycle 35 65 % tsu txd[1:0], tx_en, rxd[1:0], crs_dv, data setup to ref_clk rising edge 4 ns thold txd[1:0]. tx_en, rxd[1:0], crs_dv, data hold from ref_clk rising edge 2 ns ref_clk tx_en txd(1) txd(0) sfd preamble data 0 1 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x 0 x 0 0 0 0 0 0 0 0 0 0 x 1 0 0 0 x x x x 0 x ref_clk crs_dv rxd(1) rxd(0) sfd preamble data 0 1 1 0 0 0 0 0 0 1 1 1 1 1 x x x x x 0 x 0 0 0 0 0 0 0 0 0 0 x 1 0 0 0 x x x x 0 x /k/ /j/
olive plus specification admtek incorporated 1f, no 9, industrial e. 9 th road, sbip, hsin-chu tel : (03)578-8879 fax : (03)578-8871 00/04/25 version : 1.10 admtek incorporated confidential 17 ADM6308 package * hd=17.2mm * he=23.2mm he e e b 1 30 31 50 51 80 81 100 y a 2 a a 1 c l l 1 d hd symbo l inch min max nom mm min max nom a d c b a2 a1 - 0.547 0.004 0.009 0.098 0.010 0.134 0.555 0.008 0.015 0.114 - - 0.551 - 0.012 0.107 - 3.40 14.1 0.20 0.38 2.90 - - 14 - 0.30 2.72 - - 13.9 0.09 0.22 2.50 0.25 e 0.783 0.791 0.787 20.1 20.00 19.9 l l1 y e 0.018 0.063 ref - 0 0.026 bsc 0.030 0.003 7 0.024 - 3.5 ?? 0.75 0.076 7 0.60 - 3.5 0.45 1.60 ref - 0 0.65 bsc admtek plus olive ADM6308 xxxxxxxxxxxxxxxx

▲Up To Search▲

Price & Availability of ADM6308

	To Download ADM6308 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .